Dear Carmine,

thank you for the excellent book — it is very helpful to me in preparing a new embedded systems course!

I would like to suggest a small correction for Section 1.1.1.5. The text currently describes branch prediction techniques as follows:

“The idea behind these techniques is that the CPU starts fetching and decoding both the instructions following the branching and the ones that would be reached if the branch were to happen.”

This description more accurately characterizes dual-path (eager) execution — a technique where the processor fetches both the fall-through and the branch-target instructions and discards the wrong path after the branch condition is resolved. This is a distinct technique from branch prediction, which uses the history of past branch outcomes (e.g., a 2-bit saturating counter or a Branch History Table) to predict which single path will be taken and speculatively executes only that path. A misprediction causes a pipeline flush.

As I understand, dual-path execution is not employed in the ARM/Cortex-M architecture. Cortex-M processors use conventional branch prediction — ranging from simple static prediction (M3/M4) to dynamic prediction with a Branch Target Buffer (M7). Describing the ARM approach as “loading both paths” may therefore mislead readers about both the terminology and the actual hardware behavior.

Maybe this could be considered in a future edition of the book.

Cheers,

Hannes.